A systematic method for synthesis of asynchronous machines using Interface Protocol Asynchronous Cell (IPAC) PAL device

Abstract

A novel method of designing asynchronous sequential circuits is introduced which lends itself to implementation by edge sensitive flip-flops in a manner that edge sensitive inputs and level sensitive signals can be combined. This method enables state-machine specifications to be systematically converted into a programme for the IPAC device. In derivation of this method use is made of differential mode state tables which specify the next state as a function of the present state and input changes. Transition equations are obtained for state variables which involve level sensitive as well as edge sensitive inputs. Narrow pulses are generated for edge sensitive inputs which can then be combined with the level sensitive inputs using the PAL structure of the IPAC to clock the edge activated flip-flops of this device and generate the required states.